ONNX → Analog

Run your existing ONNX models on analog hardware without changing your training pipeline.

Analog Compute Systems is building an ONNX to Analog compiler for RRAM and crossbar based accelerators. Bring your existing models onto low-power analog hardware, without firmware, driver, or kernel engineering.

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Hardware-agnostic analog compiler
No changes to your training pipeline
Target RRAM & crossbar accelerators
Exportable ACS Pilot Pack (.zip) for your hardware team

How it works

From ONNX graph to analog execution package.

ACS sits between your trained model and your analog hardware, handling parsing, mapping, quantization, and crossbar scheduling.

①

Upload ONNX model

Start with any ONNX compatible model: vision, language, or reinforcement learning. ACS analyzes the full graph structure, operators, and tensor layout.

②

Compile to ACS-IR

The compiler converts your ONNX graph into ACS-IR: a hardware agnostic intermediate representation tuned for analog crossbar execution.

③

Deploy to analog hardware

ACS emits a deployment package for your analog accelerator: crossbar maps, tile allocations, and pulse lookup tables ready for hardware teams.

Technology

A compiler stack built for analog crossbars.

Designed for very large graphs, sparse connectivity, and real-world analog constraints like device variability, noise, and limited precision.

Model operations summary

Total operations

1355

Unique op types

11

Parameters

23.4M

MatMul42%
Conv31%
Relu / Gelu12%
LayerNorm7%
Other8%

ACS flags numerically sensitive regions for analog-aware mapping and quantization.

{
  "nodes": [
    {
      "name": "MatMul_13",
      "op": "MatMul",
      "inputs": ["input_4", "W_13"],
      "outputs": ["out_13"]
    },
    {
      "name": "Relu_14",
      "op": "Relu",
      "inputs": ["out_13"],
      "outputs": ["out_14"]
    }
  ],
  "meta": {
    "onnx_version": "1.14",
    "num_nodes": 1355
  }
}

input_4 ──▶ MatMul_13 ──▶ Relu_14 ──▶ ...

[ blocks mapped to crossbars ]
Tile 0: rows 0–255  · MatMul_0–7
Tile 1: rows 256–511 · MatMul_8–15
...

{
  "target": "acs_ref_sim_v0_1",
  "chip": {
    "tiles": [
      {
        "tile_id": 0,
        "xbars": [
          {
            "xbar_id": 0,
            "blocks": [
              {
                "tensor": "W_13",
                "row_start": 0,
                "row_end": 3,
                "col_start": 0,
                "col_end": 2,
                "storage": "frozen"
              }
            ]
          }
        ]
      }
    ]
  }
}

Efficiency

AI That Runs Cooler, Lighter, and Longer

Analog compute dramatically reduces energy consumption by performing matrix multiply operations directly inside the memory array, eliminating the data movement that dominates power usage in digital accelerators.

Lower Power

Analog crossbars exploit the physics of Ohm’s and Kirchhoff’s laws to perform massively parallel MAC operations using far less energy than digital FP16/FP32 execution.

Longer Battery Life

Wearables, IoT devices, drones, and edge sensors can run advanced models without thermal throttling or excessive power draw, enabling new classes of always-on AI applications.

Sustainable AI Deployment

By reducing data movement and digital switching, analog accelerators cut operational power requirements and cooling needs, dramatically lowering the cost of AI at scale.

Hardware Targets

Designed for Modern Analog Accelerators

ACS outputs hardware agnostic deployment packages compatible with emerging RRAM, PCM, and mixed-signal crossbar devices.

⛁

RRAM Accelerators

Resistive RAM crossbar arrays for high-density analog MAC.

✧

PCM / Memristor Devices

Phase change and memristive cells used as analog weight storage.

☷

Mixed-Signal Crossbars

Hybrid digital/analog tiles that execute in-memory matrix multiplies.

◎

Neuromorphic Cores

Spiking and event driven analog compute fabrics.

▣

Edge Analog AI Modules

Low-power accelerators for wearables, IoT, and embedded systems.

Compiler stack

End to end pipeline for analog inference.

ONNX parser

Supports large graphs and transformer style models. Handles shapes, dtypes, and subgraphs.

ACS-IR

Intermediate representation tailored to analog crossbar arrays, tiles, and blocks.

Crossbar mapping

Places tensors across devices and tiles, respecting array dimensions and routing constraints.

Execution package

Emits artifacts your hardware team can simulate, implement, and tape out.

The pilot stack uses ACS-IR v0.1, ACS Program v0.2, and the ACS Ref Simulator v0.2 to map and evaluate ONNX models on your analog profile.

Pilot program

$25K paid pilot · 4 weeks

For chip companies and hardware teams building RRAM, PCM, or crossbar accelerators who want to run real customer models on silicon.

Ingest one production ONNX model of your choice.
Create a hardware specific ACS profile from your crossbar/tile specs.
Compile the model to ACS-IR v0.1 and ACS Program v0.2.
Generate a mapping plan (tile usage, crossbar utilization, capacity headroom).
Run baseline latency & energy estimates with the ACS Ref Simulator.

Pilot deliverables

acs_profile_company_v0.1.json (hardware profile)
acs_ir.json (ACS-IR v0.1)
program.json (ACS Program v0.2)
mapping_plan.json (tile / crossbar fit & utilization)
runtime_sim.json (latency & energy summary)
metadata.json & README.md
ACS Pilot Pack (.zip) and a final pilot report + review call

Request Pilot Access

FAQ

Frequently Asked Questions

Do I need my own analog hardware to start? +

No. ACS can analyze and compile ONNX models even before hardware is available. Most teams begin with model analysis, ACS-IR, and mapping proposals.

What model types are supported? +

Any ONNX-compatible model: vision, language, RL, transformers, CNNs, and custom architectures.

Do we need to retrain or modify our models? +

No. ACS is fully model preserving. You don’t need to retrain, do quantization aware training, or change your training pipeline.

How long does the pilot take? +

The structured pilot runs about 4 weeks for one ONNX model and one hardware profile.

Can ACS work with early stage hardware? +

Yes. ACS produces hardware agnostic ACS-IR and crossbar mappings that can adapt as your device matures.

Is ACS tied to a specific chip vendor? +

No. ACS is independent and supports any analog or mixed-signal accelerator that accepts ONNX to derived workloads.

About Analog Compute Systems

Analog Compute Systems (ACS) is a software company that built a compiler stack for the next generation of analog AI hardware. We believe the future of efficient AI won’t come from increasingly larger digital chips, but from compute architectures that leverage the underlying physics of memory and analog signal flow.

ACS is developing the missing software layer between ONNX models and analog crossbar accelerators providing a hardware agnostic compiler that lets AI teams deploy existing models onto analog devices without rewriting code, retraining networks, or adopting new tooling.

Founder

Vanjuan Vladimirov

Vanjuan Vladimirov is the founder of Analog Compute Systems, leading the development of a modern compiler stack designed for emerging analog AI hardware. His work focuses on bridging the gap between AI research teams and analog accelerator manufacturers enabling models to run on RRAM and crossbar based devices without requiring changes to existing tools, training pipelines, or model architectures.

ACS is currently working with early hardware and system partners ahead of a broader pilot program.

Ready to explore a pilot?

Share a bit about your hardware, timelines, and the models you care about most.

Contact

Email: founder@analogcomputesystems.com
Location: Indio, California